Speaker: Chen Deming (professor of University of Illinois at Urbana-Champaign, U.S.)
Theme: design, compiling and acceleration of deep neural network in the applications of Internet of Things (IoT)
When: 16:00, Oct. 22 (Tuesday)
Where:J2-103, Jiulonghu Campus
Hosted by: Chieng-Shiung Wu College of SEU
About the speaker:
Dr. Chen Deming, the holder of Bachelor’s Degree in Computer Science from the University of Pittsburgh and Master’s Degree and Ph.D. in Computer Science from the University of California, is currently serving University of Illinois at Urbana-Champaign as a Professor at the Department of Electronics and Computer Engineering. His current researches cover the system-level and advanced synthesis, machine learning, GPU, reconfigurable computing and hardware security, etc.. He was once invited to deliver more than 110 related lectures. Dr. Chen once received the Arnold O. Beckman Research Award from UIUC, the NSF Professional Award, 8 Best Paper Awards and ACM SIGDA Outstanding New Teacher Award; besides, he was once granted IBM Instructor Award twice, led the team to win the first prize twice in DAC International System Design Competition in the field of Internet of Things and was appraised as the excellent teacher. In addition, he is a scholar of Donald Bygweitzer School of Engineering, an IEEE member, an ACM Distinguished Speaker and the editor of ACM TREES. He has participated in the foundation of several companies such as Yingrui Internet of Things.
[Reasons for recommendation]
Today, various deep neural networks (DNNs) are widely applied to the driving of the Internet of Things. These IoT applications rely on the efficient hardware implementation of DNN. In this lecture, Professor Chen Deming will analyze several challenges faced by AI and IoT applications in mapping DNNs to hardware accelerators, especially how FPGA accelerates DNN as loaded on the cloud and the edge devices. As FPGA features difficulty in programing and optimization, Professor Chen will introduce a range of effective design techniques to achieve high performance and energy efficient DNN on the FPGA, including automated hardware/software co-design, configurable use of DNN IP cores, resources allocation between DNN layers, intelligent pipeline scheduling, DNN restoration and retraining. Professor Chen will display several design solutions, including a long-term circular convolutional network (LRCN) for video subtitles and an Inception module for face recognition (GoogleNet).